Two high-speed, PECL/LVPECL clock fanout buffers from Micrel Semiconductor are said to meet ultra-low, skew, jitter, and redundant switchover requirements in SONET/SDH communication systems, high-end enterprise server applications, and ATE systems. The company’s SY89830U is a fully differential PECL/LVPECL 1:4 fanout buffer with a differential 2:1 MUX input.
The device reportedly is guaranteed to operate down to +2.3 V, thus making it an ideal solution for low-voltage, +2.5-V PECL clock distribution systems.
The 3.3 V/5 V SY100EP15V is also a 1:4 PECL/LVPECL fanout buffer with a 2:1 MUX input, but one of the inputs is single-ended, and the other input to the MUX is differential. In addition, the SY100EP15V includes a VBB reference voltage for single-ended inputs or a.c.-coupled applications. Both fanout buffers include a synchronous enable function that forces all outputs into a fixed logic state, reportedly without any possibility of short, runt pulses. To maintain extremely tight timing budgets over all system conditions, the company says that both buffers are guaranteed over temperature and supply voltage.
Maximum frequency is greater than 2.5 GHz, within-device skew is less than 25 ps, propagation delay is less than 450 ps, and output rise and fall time is less than 225 ps. In addition, propagation delay is said to be extremely stable over the entire industrial temperature range.