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Serializer/Deserializer Technology
June 2007
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The company’s second-generation FIN324C uSerDes-uLP (ultra-low-power) series of serializer/deserializer technology is said to offer the industry’s lowest current consumption (~4 mA at 5.44 MHz), eliminate the need for external timing-reference devices, and support dual displays. This is said to help designers save battery power, increase design flexibility, and reduce part count in the latest cell phones, MP3 players, and other small-form-factor display applications. The technology is available in ultrasmall BGA and MLP packages. The company codesigned the new technology with key cell phone manufacturers to optimize energy consumption and minimize noise in increasingly slim, compact applications. Key feature enhancements of the second-generation series include the elimination of the internal Phase-Lock Loop (PLL) to reduce current consumption and eliminate the need for an external clock. Dual-interface capability (R/W microcontroller, pixel, and/or SPI) is said to provide increased design flexibility. Fairchild Semiconductor

Fairchild Semiconductor


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