One of the challenges in sensing technology is to combine the different requirements of microelectromechanical systems (MEMS) with that of conventional electronic circuitry at the wafer level. VTI Technologies (www.vti.fi) of Vantaa, Finland, is working to jump that hurdle to create new sensing applications for a wide range of handheld devices.
In the first phase of its development, VTI says it has been able to use currently available techniques to make smaller, lower-cost devices. In the second phase, the company is looking at new manufacturing technologies that will allow more-complex sensing devices to be made using wafer-level integrations with the benefits of lower-cost volume production and small size. “We see that in the long run, the size and some cost elements of conventional overmolded packaging of MEMS will reach the ultimate limit and a new technical approach is needed,” explains Heikki Kuisma, vice president of research. “[For example], 0.5-mm thickness is difficult without wafer-level package (WLP), and small footprint and wafer-based handling in packaging and testing will eventually lower the cost of the devices.”
The first phase of R&D, completed last year, investigated the potential of heterogeneous integration. The company’s approach has been to maintain the benefits of manufacturing MEMS devices and ASICs on separate wafers to allow full testing of both types of devices before wafer-level integration takes place. “It is important to get a decent yield and reduce the total test complexity,” Kuisma says. “We don’t want to place a good IC on bad MEMS and vice versa. It is more important to test the MEMS device before attaching an IC to it.”
For the company’s chip-on-MEMS integration concept, thinned ASICs chips are flip-chipped onto the MEMS wafer in known good locations (as pictured). Redistribution and isolation layers are applied to the MEMS wafer, solder points are provided for external connection before the ASICs are added, and the MEMS and ASICs chips are then passivated using an underfill expoxy layer.
According to Kuisma, the reason that no one has been able to achieve this level of integration is due to drawbacks in vacuum encapsulation of conventional MEMS devices. “[This] is done by sealing an encapsulation wafer to the MEMS wafer by using so-called glass frit bonding,” he explains. “Electrical contacts from the enclosed space are fed out using horizontal vias. The external contacts lie on the MEMS wafer and are exposed at a cutout of the encapsulation wafer. The encapsulated wafer surface is not planar and, thus, doesn’t allow any further processing.”
VTI, however, has developed an encapsulation technology said to consume much less area for sealing and enable vertical vias through the encapsulation wafer. “The electrical contacts don’t consume any extra area,” Kuisma says. “The seal area is typically only 20% of the device area. But the really important thing is that the encapsulation wafer remains planar and allows further processing—redistribution layers, flip-chipping of ASICs, ball drop.”
VTI has successfully constructed and tested a demonstration component with a footprint of 4 mm2 and a height of less than 1 mm. The next step is to produce complex sensing components that combine MEMS sensing elements with several ASICs chips. The end result could mean MEMS devices that are a third of their current sizes and smarter sensors with more input/output features, onboard microprocessing, and radio communications in applications such as portable computers, navigation systems, and digital cameras.
